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<a name="details" id="details"></a><h2 class="groupheader">Overview</h2>
<div class="textblock"><p>This file implements the Intel CFI Version of the XFlash Library. </p>
<dl class="section note"><dt>Note</dt><dd></dd></dl>
<ul>
<li>Special consideration has to be given to varying data bus widths. To boost performance, multiple devices in parallel on the data bus are accessed in parallel. Therefore to reduce complexity and increase performance, many local primitive functions are duplicated with the only difference being the width of writes to the devices. <br/>
<br/>
 Even with the performance boosting optimizations, the overhead associated is rather high due to the general purpose nature of its design. <br/>
<br/>
 Flash block erasing is a time consuming operation with nearly all latency occurring due to the devices' themselves. It takes on the order of 1 second to erase each block. <br/>
<br/>
 Writes by comparison are much quicker so library overhead becomes an issue. The write algorithm has been optimized for bulk data programming and should provide relatively better performance.</li>
<li>The code/comments refers to WSM frequently. This stands for Write State Machine. WSM is the internal programming engine of the devices.</li>
<li>This library and the underlying Intel flash memory does not allow re- programming while code is executing from the same memory.</li>
<li>If hardware is flakey or fails, then this library could hang a thread of execution.</li>
</ul>
<pre></pre><pre>MODIFICATION HISTORY:</pre><pre>Ver   Who  Date     Changes
</p>
<hr/>
<p>
1.00a rmm  10/25/07 First release
1.00a mta  10/25/07 Updated to flash library
1.01a ksu  04/10/08 Added support for AMD CFI Interface
1.02a ksu  06/16/09 Added support for multiple banks in Intel flash
                    Added Reset Bank function
                    Added support for 0xF0 reset command
                    Added support for Xilinx Platform Flash XL.
                    Added XFL_DEVCTL_SET_CONFIG_REG IOCTL to write to the
                    Configuration Register of the Xilinx Platform Flash XL
                    which can be used to set the Flash in Sync/Async mode.
                    The Xilinx Platform Flash XL is set to Async mode during
                    the initialization of the library.
                    Added bank(s) reset function at the top of the read
                    function.
                    Updated Lock and Unlock operations for multiple blocks.
1.03a ksu  10/07/09 Added support for large buffer size flash (CR535564)
3.01a srt  03/02/12 Added support for Micron G18 Flash device to fix
              CRs 648372, 648282.
              Modified XFlashIntel_Reset function to reset all the
              partitions.
3.02a srt  05/30/12 Changed Implementation for Micron G18 Flash, which
              fixes the CR 662317.
              CR 662317 Description - Xilinx Platform Flash on ML605
              fails to work.
3.03a srt  11/04/12 Fixed CR 679937 -
              Description: Non-word aligned data write to flash fails
              with AXI interface.
4.1     nsk  08/06/15 Fixed CR 835008.
4.7     akm  07/23/19 Initialized Status variable to XST_FAILURE.
4.10    akm  07/14/23 Added support for system device-tree flow.
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